Geçtiğimiz dönem içerisinde finansal olarak zor günler geçiren ve özellikle SoftMenü teknolojisi sayesinde overclock sektörünün gelişimine yaptığı ciddi katkı ile tanınan ve sevilen Abit, Universal grubunun çatısı altına girdikten sonra tekrar eski günlerine dönüş yapmak istediğinin sinyallerini veren yeni ve iddialı anakartlarını arka arkaya duyurmaya başladı ve devam ediyor. Firmanın hazırladığı ve iddialı olduğunu en son modeli ise IP35 Pro Off Limits.
Abit IP35 Pro tahmin edebileceğiniz gibi Intel'in yeni nesil P35 yonga setini kullanıyor. Bu sayede anakart şu an satılmakta olan tüm Core 2 işlemcilerin yanı ısra Temmuz ayında gelecek olan 1333MHz fsb'ye sahip işlemcilere ve 2008 başında piyasaya çıkması beklenen 45nm üretim teknolojisine sahip işlemcilere de destek vermekte. Anakart sahip olduğu 4 adet DIMM slotu üzerinden 8GB'a kadar DD-2 800MHz bellek desteği sunmakta. Çift PCIe X16 slotuna sahip olan anakart doğal olarak ATi'nin Crossfire teknolojisine de destek sağlamakta.
Voltaj regülatörleri, kuzey ve güney köprülerini kapsayan bakır alaşımlı ısı iletim teknolojisini esas alan ve pasif soğutma kullanan Abit IP35 Pro üzerinde ayrıca kullanılan katı kapasitörler (%100 Japon) de dikkatlerden kaçmıyor. Anakart üzerinde yine Abit'e özgü olan harici CCMOS Switch'i de yer almakta. Bu sayede başarısız hız aşırtma girişimlerinden sonra kullanıcılar kolaylıkla CMOS resetlemesi yapılabiliyor. 2 adet PCIe X16 slotunun yanı sıra anakart üzirinde ek olarak 3adet PCI ve 1 adet te PCIe X1 slotu bulunuyor.
Abit IP35 Pro'nun dikkat çeken diğer özellikleri arasında 2 adet gigabit lan desteği, 7.1 kanal yüksekt tanımlı ses yongası, 6 adet SATA-2 konnektörü (RAID0/1/5/10) ve bolca USB 2.0 desteği yer almakta. Tabii anakart üzerine harici SATA desteği koymayı da Abit ihmal etmemiş. Quad-GT modeli ile yeniden eski günlere dönüş sinyalleri veren Abit, IP35 Pro modeli ile de iddiasını geliştirirek devam ettirme peşinde. Anakartın fiyatı ve piyasaya çıkış tarihi konusunda ise net bir bilgi bulunmuyor.
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Eposta ile Paylaşın başlıklı bu arkadaşınıza postalayın.Bu haberi, mobil uygulamamızı kullanarak indirip, istediğiniz zaman (çevrim dışı bile) okuyabilirsiniz:
bir abit kullanıcısıyım AN8 SLI bugüne kadar hiç bir problem yaşamadım
post kodları ilgili olarak bende olan kodları ekleyeyim dedim
ingilizcem olmadığı için çeviremedim kusura bakmayın :)
AWARD POST Code Definition:
POST (hex) Description
CF Test CMOS R/W functionality
C0 Early chipset initialization:
-Disable shadow RAM
-Disable L2 cache (socket 7 or below)
-Program basic chipset registers
C1 Detect memory
-Auto-detection of DRAM size, type and ECC
-Auto-detection of L2 cache (socket 7 or below)
C3 Expand compressed BIOS code to DRAM
C5 Call chipset hook to copy BIOS back to E000 & F000 shadow RAM
01 Expand the Xgroup codes locating in physical address 1000:0
03 Initial Superio_Early_Init switch
05 1. Blank out screen
2. Clear CMOS error flag
07 1. Clear 8042 interface
2. Initialize 8042 self-test
08 1. Test special keyboard controller for Winbond 977 series Super I/O chips
2. Enable keyboard interface
0A 1. Disable PS/2 mouse interface (optional)
2. Auto detect ports for keyboard & mouse followed by a port & interface swap (optional)
3. Reset keyboard for Winbond 977 series Super I/O chips
0E Test F000h segment shadow to see whether it is R/W-able or not. If test fails, keep beeping the speaker
10 Auto detect flash type to load appropriate flash R/W codes into the run time area in F000 for ESCD & DMI support
12 Use walking 1.s algorithm to check out interface in CMOS circuitry. Also set real-time clock power status, and then check for override
14 Program chipset default values into chipset. Chipset default values are MODBINable by OEM customers
16 Initial onboard clock generator if Early_Init_Onboard_Generator is defined. See also POST 26.
18 Detect CPU information including brand, SMI type (Cyrix or Intel) and CPU level (586 or 686)
1B Initial interrupts vector table. If no special specified, all H/W interrupts are directed to SPURIOUS_INT_HDLR & S/W interrupts to SPURIOUS_soft_HDLR.
1D Initial EARLY_PM_INIT switch
User.s Manual G-2 Appendix G
1F Load keyboard matrix (notebook platform)
21 HPM initialization (notebook platform)
23 1. Check validity of RTC value: e.g. a value of 5Ah is an invalid value for RTC minute.
2. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value instead.
24 Prepare BIOS resource map for PCI & PnP use. If ESCD is valid, take into consideration of the ESCD.s legacy information.
25 Early PCI Initialization:
-Enumerate PCI bus number.
-Assign memory & I/O resource
-Search for a valid VGA device & VGA BIOS, and put it into C000:0
26 1. If Early_Init_Onboard_Generator is not defined Onboard clock generator initialization. Disable respective clock resource to empty PCI & DIMM slots.
2. Init onboard PWM
3. Init onboard H/W monitor devices
27 Initialize INT 09 buffer
29 1. Program CPU internal MTRR (P6 & PII) for 0-640K memory address.
2. Initialize the APIC for Pentium class CPU.
3. Program early chipset according to CMOS setup. Example: onboard IDE controller.
4. Measure CPU speed.
2B Invoke Video BIOS
2D 1. Initialize double-byte language font (Optional)
2. Put information on screen display, including Award title, CPU type, CPU speed, full screen logo.
33 Reset keyboard if Early_Reset_KB is defined e.g. Winbond 977 series Super I/O chips. See also POST 63.
35 Test DMA Channel 0
37 Test DMA Channel 1.
39 Test DMA page registers.
3C Test 8254
3E Test 8259 interrupt mask bits for channel 1
40 Test 8259 interrupt mask bits for channel 2
43 Test 8259 functionality
47 Initialize EISA slot
49 1. Calculate total memory by testing the last double word of each 64K page
2. Program writes allocation for AMD K5 CPU
4E 1. Program MTRR of M1 CPU
2. Initialize L2 cache for P6 class CPU & program CPU with proper cacheable range
3. Initialize the APIC for P6 class CPU
4. On MP platform, adjust the cacheable range to smaller one in case the cacheable ranges between each CPU are not identical
50 Initialize USB
52 Test all memory (clear all extended memory to 0)
53 Clear password according to H/W jumper (Optional)
AN8 Series POST Code Definition G-3
55 Display number of processors (multi-processor platform)
57 Display PnP logo
Early ISA PnP initialization
-Assign CSN to every ISA PnP device
59 Initialize the combined Trend Anti-Virus code
5B (Optional Feature) Show message for entering AWDFLASH.EXE from FDD (optional)
5D 1. Initialize Init_Onboard_Super_IO
2. Initialize Init_Onbaord_AUDIO
60 Okay to enter Setup utility; i.e. not until this POST stage can users enter the CMOS setup utility
63 Reset keyboard if Early_Reset_KB is not defined
65 Initialize PS/2 Mouse
67 Prepare memory size information for function call: INT 15h ax=E820h
69 Turn on L2 cache
6B Program chipset registers according to items described in Setup & Auto-configuration table
6D 1. Assign resources to all ISA PnP devices
2. Auto assign ports to onboard COM ports if the corresponding item in Setup is set to .AUTO.
6F 1. Initialize floppy controller
2. Set up floppy related fields in 40:hardware
75 Detect & install all IDE devices: HDD, LS120, ZIP, CDROM .
76 (Optional Feature)
Enter AWDFLASH.EXE if:
-AWDFLASH is found in floppy drive
-ALT+F2 is pressed
77 Detect serial ports & parallel ports.
7A Detect & install co-processor
7C Init HDD write protect
7F Switch back to text mode if full screen logo is supported
-If errors occur, report errors & wait for keys
-If no errors occur or F1 key is pressed to continue: Clear EPA or customization logo
E8POST.ASM starts
82 1. Call chipset power management hook
2. Recover the text font used by EPA logo (not for full screen logo)
3. If password is set, ask for password
83 Save all data in stack back to CMOS
84 Initialize ISA PnP boot devices
85 1. USB final Initialization
2. Switch screen back to text mode
87 NET PC: Build SYSID Structure
89 1. Assign IRQs to PCI devices
2. Set up ACPI table at top of the memory.
User.s Manual G-4 Appendix G
8B 1. Invoke all ISA adapter ROMs
2. Invoke all PCI ROMs (except VGA)
8D 1. Enable/Disable Parity Check according to CMOS setup
2. APM Initialization
8F Clear noise of IRQs
93 Read HDD boot sector information for Trend Anti-Virus code
gerçekten de bizim millet tutturmuş bir asus diye öyle gidiyo.
300 e satılacak kart marka ismi asus olunca 500 e satılıyor.
kadıköy de millete bakıyorum da asus anakart diye tutturuyo ya.
evet asus kaliteli board lar yapar.
ama efsane bir marka olan abit le kıyaslamak olmaz.[>:]
bir abit kullanıcısıyım AN8 SLI bugüne kadar hiç bir problem yaşamadım
post kodları ilgili olarak bende olan kodları ekleyeyim dedim
ingilizcem olmadığı için çeviremedim kusura bakmayın :)
AWARD POST Code Definition:
POST (hex) Description
CF Test CMOS R/W functionality
C0 Early chipset initialization:
-Disable shadow RAM
-Disable L2 cache (socket 7 or below)
-Program basic chipset registers
C1 Detect memory
-Auto-detection of DRAM size, type and ECC
-Auto-detection of L2 cache (socket 7 or below)
C3 Expand compressed BIOS code to DRAM
C5 Call chipset hook to copy BIOS back to E000 & F000 shadow RAM
01 Expand the Xgroup codes locating in physical address 1000:0
03 Initial Superio_Early_Init switch
05 1. Blank out screen
2. Clear CMOS error flag
07 1. Clear 8042 interface
2. Initialize 8042 self-test
08 1. Test special keyboard controller for Winbond 977 series Super I/O chips
2. Enable keyboard interface
0A 1. Disable PS/2 mouse interface (optional)
2. Auto detect ports for keyboard & mouse followed by a port & interface swap (optional)
3. Reset keyboard for Winbond 977 series Super I/O chips
0E Test F000h segment shadow to see whether it is R/W-able or not. If test fails, keep beeping the speaker
10 Auto detect flash type to load appropriate flash R/W codes into the run time area in F000 for ESCD & DMI support
12 Use walking 1.s algorithm to check out interface in CMOS circuitry. Also set real-time clock power status, and then check for override
14 Program chipset default values into chipset. Chipset default values are MODBINable by OEM customers
16 Initial onboard clock generator if Early_Init_Onboard_Generator is defined. See also POST 26.
18 Detect CPU information including brand, SMI type (Cyrix or Intel) and CPU level (586 or 686)
1B Initial interrupts vector table. If no special specified, all H/W interrupts are directed to SPURIOUS_INT_HDLR & S/W interrupts to SPURIOUS_soft_HDLR.
1D Initial EARLY_PM_INIT switch
User.s Manual G-2 Appendix G
1F Load keyboard matrix (notebook platform)
21 HPM initialization (notebook platform)
23 1. Check validity of RTC value: e.g. a value of 5Ah is an invalid value for RTC minute.
2. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value instead.
24 Prepare BIOS resource map for PCI & PnP use. If ESCD is valid, take into consideration of the ESCD.s legacy information.
25 Early PCI Initialization:
-Enumerate PCI bus number.
-Assign memory & I/O resource
-Search for a valid VGA device & VGA BIOS, and put it into C000:0
26 1. If Early_Init_Onboard_Generator is not defined Onboard clock generator initialization. Disable respective clock resource to empty PCI & DIMM slots.
2. Init onboard PWM
3. Init onboard H/W monitor devices
27 Initialize INT 09 buffer
29 1. Program CPU internal MTRR (P6 & PII) for 0-640K memory address.
2. Initialize the APIC for Pentium class CPU.
3. Program early chipset according to CMOS setup. Example: onboard IDE controller.
4. Measure CPU speed.
2B Invoke Video BIOS
2D 1. Initialize double-byte language font (Optional)
2. Put information on screen display, including Award title, CPU type, CPU speed, full screen logo.
33 Reset keyboard if Early_Reset_KB is defined e.g. Winbond 977 series Super I/O chips. See also POST 63.
35 Test DMA Channel 0
37 Test DMA Channel 1.
39 Test DMA page registers.
3C Test 8254
3E Test 8259 interrupt mask bits for channel 1
40 Test 8259 interrupt mask bits for channel 2
43 Test 8259 functionality
47 Initialize EISA slot
49 1. Calculate total memory by testing the last double word of each 64K page
2. Program writes allocation for AMD K5 CPU
4E 1. Program MTRR of M1 CPU
2. Initialize L2 cache for P6 class CPU & program CPU with proper cacheable range
3. Initialize the APIC for P6 class CPU
4. On MP platform, adjust the cacheable range to smaller one in case the cacheable ranges between each CPU are not identical
50 Initialize USB
52 Test all memory (clear all extended memory to 0)
53 Clear password according to H/W jumper (Optional)
AN8 Series POST Code Definition G-3
55 Display number of processors (multi-processor platform)
57 Display PnP logo
Early ISA PnP initialization
-Assign CSN to every ISA PnP device
59 Initialize the combined Trend Anti-Virus code
5B (Optional Feature) Show message for entering AWDFLASH.EXE from FDD (optional)
5D 1. Initialize Init_Onboard_Super_IO
2. Initialize Init_Onbaord_AUDIO
60 Okay to enter Setup utility; i.e. not until this POST stage can users enter the CMOS setup utility
63 Reset keyboard if Early_Reset_KB is not defined
65 Initialize PS/2 Mouse
67 Prepare memory size information for function call: INT 15h ax=E820h
69 Turn on L2 cache
6B Program chipset registers according to items described in Setup & Auto-configuration table
6D 1. Assign resources to all ISA PnP devices
2. Auto assign ports to onboard COM ports if the corresponding item in Setup is set to .AUTO.
6F 1. Initialize floppy controller
2. Set up floppy related fields in 40:hardware
75 Detect & install all IDE devices: HDD, LS120, ZIP, CDROM .
76 (Optional Feature)
Enter AWDFLASH.EXE if:
-AWDFLASH is found in floppy drive
-ALT+F2 is pressed
77 Detect serial ports & parallel ports.
7A Detect & install co-processor
7C Init HDD write protect
7F Switch back to text mode if full screen logo is supported
-If errors occur, report errors & wait for keys
-If no errors occur or F1 key is pressed to continue: Clear EPA or customization logo
E8POST.ASM starts
82 1. Call chipset power management hook
2. Recover the text font used by EPA logo (not for full screen logo)
3. If password is set, ask for password
83 Save all data in stack back to CMOS
84 Initialize ISA PnP boot devices
85 1. USB final Initialization
2. Switch screen back to text mode
87 NET PC: Build SYSID Structure
89 1. Assign IRQs to PCI devices
2. Set up ACPI table at top of the memory.
User.s Manual G-4 Appendix G
8B 1. Invoke all ISA adapter ROMs
2. Invoke all PCI ROMs (except VGA)
8D 1. Enable/Disable Parity Check according to CMOS setup
2. APM Initialization
8F Clear noise of IRQs
93 Read HDD boot sector information for Trend Anti-Virus code
94 1. Enable L2 cache
2. Program Daylight Saving
3. Program boot up speed
4. Chipset final initialization.
5. Power management final initialization
6. Clear screen & display summary table
7. Program K6 write allocation
8. Program P6 class write combining
95 Update keyboard LED & typematic rate
96 1. Build MP table
2. Build & update ESCD
3. Set CMOS century to 20h or 19h
4. Load CMOS time into DOS timer tick
5. Build MSIRQ routing table
FF Boot attempt (INT 19h)
AN8 Series POST Code Definition G-5
AC2003 POST Code Definition:
POST (hex) Description
Power On Sequence
8.1. Start power on sequence
8.2. Enable ATX power supply
8.3. ATX power supply ready
8.4. DDR voltage ready
8.5. Setup PWM for CPU core voltage
8.6. Assert PWM for CPU core voltage
8.7. Check CPU core voltage
8.8. CPU core voltage ready
8.9. Initial clock generator IC
8.A. North Bridge chipset voltage ready
8.B. AGP voltage ready
8.C. 3VDUAL voltage ready
8.D. VDDA 2.5V voltage ready
8.D. GMCHVTT voltage ready
8.E. Check CPU fan speed
8.F. Assert all power ready
9.0. Complete uGuru initial process
AWARD BIOS take over booting job
Power Off Sequence
9.1. Start power off sequence
9.2. De-Assert all power
9.3. Se-Assert power on
9.4. De-Assert LDT Bus power
9.5. De-Assert PWM for CPU core voltage
9.6. De-Assert CPU core voltage
9.7. Check CPU core voltage
9.8. De-Assert ATX power supply
9.9. Complete power off sequence
Others
F.0. Button reset
F.1. SoftMenu reset
F.2. Power on sequence timeout
F.3. Power off sequence timeout
umarım ülkemizde satışa sunulur.